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| GTLP6C816 GTLP-to-TTL 1:6 Clock Driver June 1998 Revised October 1998 GTLP6C816 GTLP-to-TTL 1:6 Clock Driver General Description The GTLP6C816 is a clock driver that provides TTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. Features s Interface between TTL and GTLP logic levels s Edge Rate Control to minimize noise on the GTLP port s Power up/down high impedance for live insertion s 1:6 fanout clock driver for TTL port s 1:2 fanout clock driver for GTLP port s TTL compatible driver and control inputs s Flow through pinout optimizes PCB layout s Open drain on GTLP to support wired-or connection s Recommended Operating Temperature -40C to +85C Ordering Code: Order Number GTLP6C816MTC Package Number MTC24 Package Description 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Descriptions Pin Names Description TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively) OEB OEA VCCT.GNDT VCC GNDG VREF OA0-OA5 OB0-OB1 Output Enable (Active LOW) GTLP Port (TTL Levels) Output Enable (Active LOW) TTL Port (TTL Levels) TTL Output Supplies (5V) Internal Circuitry VCC (5V) OBn GTLP Output Grounds Voltage Reference Input TTL Buffered Clock Outputs GTLP Buffered Clock Outputs Connection Diagram (c) 1998 Fairchild Semiconductor Corporation DS500129.prf www.fairchildsemi.com GTLP6C816 Functional Description The GTLP6C816 is a clock driver providing TTL-to-GTLP clock translation, and GTLP-to-TTL clock translation in the same package. The TTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to-TTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting for both directions. Truth Tables Inputs TTLIN H L X Inputs GTLPIN H L X OEA L L H OEB L L H Outputs OBn L H High Z Outputs OAn L H High Z Logic Diagram www.fairchildsemi.com 2 GTLP6C816 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 2) DC Output Sink Current into OA-Port IOL DC Output Source Current from OA-Port IOH DC Output Sink Current into OB-Port in the LOW State IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC ESD Rating Storage Temperature (TSTG) -50 mA +50 mA > 2000V -65C to +150C -50 mA 80 mA -48 mA 48 mA -0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V Recommended Operating Conditions (Note 3) Supply Voltage VCC Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on INA-Port and Control Pins HIGH Level Output Current (IOH) OA-Port LOW Level Output Current (IOL) OA-Port OB-Port Operating Temperature (TA) +24 mA +34 mA -40C to +85C -24 mA 0.0V to 5.5V 1.47V to 1.53V 0.98V to 1.02V 4.75V to 5.25V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: Io Absolute Maximum Rating must be observed. Note 3: Unused input must be held high or low. 3 www.fairchildsemi.com GTLP6C816 DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Typ Symbol VIH VIL VREF (Note 5) VTT (Note 5) VIK VOH OAn-Port GTLPIN Others GTLPIN Others GTLP GTL GTLP GTL VCC = 4.75V VCC = 4.75V II = -18 mA IOH = -100 A IOH = -18 mA IOH = -24 mA VOL OAn-Port VCC = 4.75V IOL = 100 A IOL = 18 mA IOL = 24 mA VOL II OBn-Port TTLIN/ Control Pins GTLPIN IOFF IOZH IOZL ICC TTLIN OAn-Port OBn-Port OAn-Port OAn or OBn Ports VI = VCC or GND ICC CIN COUT TTLIN Control Pins/GTLPIN/ TTLIN OAn-Port OBn-Port Note 4: All typical values are at VCC = 5.0V and TA = 25C. Note 5: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted to accommodate backplane impedances other than 50, within the boundaries of not exceeding the DC Absolute IOL ratings. Similarly VREF can be adjusted to compensate for changes in V TT. Test Conditions Min (Note 4) VREF +0.05 2.0 0.0 1.0 0.8 1.5 1.2 Max VTT VREF -0.05 0.8 Units V V V V -1.2 VCC-0.2 2.4 2.2 0.2 0.4 0.5 0.2 0.65 5 -5 5 -5 100 5 5 -5 7 7 7 18 20 20 6 3.7 7 7 V V V VCC = 4.75V VCC = 5.25V VCC = 5.25V VCC = 0 VCC = 5.25V VCC = 5.25V VCC = 5.25V IOL = 100 A IOL = 34 mA VI = 5.25V VI = 0V VI = VTT VI = 0 VI or VO = 0V to 5.25V VO = 5.25V VO = 1.5V VO = 0 Outputs HIGH Outputs LOW Outputs Disabled VI = VCC-2.1 VI = VCC or 0 VI = VCC or 0 VI = VCC or 0 V A A A A A mA mA pF pF VCC = 5.25V www.fairchildsemi.com 4 GTLP6C816 AC Electrical Characteristics Over recommended range of supply voltage and operating free air temperature. VREF = 1.0V (unless otherwise noted). CL = 30 pF for OBn-Port and CL = 50 pF for OAn-Port. Symbol tPLH tPHL tPLH tPHL tRISE tFALL tRISE tFALL tPZH, tPZL tPLZ , tPHZ tPLH tPHL tOSHL, tOSLH (Note 7) Common Edge Skew GTLPIN OAn Transition Time, OB Outputs (20% to 80%) Transition Time, OB outputs (20% to 80%) Transition Time, OA outputs (10% to 90%) Transition Time, OA outputs (10% to 90%) OEA OAn 0.5 0.5 1.5 1.5 OEB OBn From (Input) TTLIN To (Output) OBn Min 1.5 1.5 1.5 1.5 Typ (Note 6) 3.8 2.8 6.4 3.2 2.3 2.3 2.0 2.0 3.6 3.8 4.4 4.0 0.2 6.5 ns 6.5 6.5 ns 6.0 1.0 ns Max 6.0 ns 5.0 10.5 ns 6.0 ns ns ns ns Units Note 6: All typical values are at VCC = 5.0V and TA = 25C. Note 7: Skew specs are given for specific worst case VCC Temp. Skew values between the OBn outputs could vary on the backplane due to loading and impedance seen by the device. 5 www.fairchildsemi.com GTLP6C816 Test Circuit and Timing Waveforms Test Circuit for A Outputs Test Circuit for B Outputs Note A: CL includes probes and jig capacitance. Note B: For B-Port CL = 30 pF is used for worst case. Note A: CL includes probes and jig capacitance. Voltage Waveforms Enable and Disable Times A-Port Voltage Waveforms Propagation Delay (Vm = VCC/2 for A-Port and 1.0 for B-Port) www.fairchildsemi.com 6 GTLP6C816 GTLP-to-TTL 1:6 Clock Driver Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. |
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